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TFPGA's avatar
TFPGA
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7 years ago
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External memory Interface Intel Cyclone 10 FPGA IP configure DATA bus size from Avalon MM interface

I am migrating a system from an old Arria II to a Cyclone 10 GX, so I need to migrate from a DDR2 interface connected to a Avalon MM with an interface of 128 bits. I would like to use this controlle...
  • NurAida_A_Intel's avatar
    NurAida_A_Intel
    7 years ago

    Hi ADona,

    Cyclone 10 GX package only support DDR3 x40 with ECC. This information cover in “Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook” page 166.

    So, you need to turn on the “Enable Error Detection and Correction Logic with ECC” under the “Controller” setting in order to use DDR3 x40.

    Another option is you can use 32 DQ width and you can see now the amm interface become 256bits.

    Hope this helps.

    Thanks

    Regards,

    NAli1

NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi ADona,

Cyclone 10 GX package only support DDR3 x40 with ECC. This information cover in “Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook” page 166.

So, you need to turn on the “Enable Error Detection and Correction Logic with ECC” under the “Controller” setting in order to use DDR3 x40.

Another option is you can use 32 DQ width and you can see now the amm interface become 256bits.

Hope this helps.

Thanks

Regards,

NAli1

  • TFPGA's avatar
    TFPGA
    Icon for New Contributor rankNew Contributor
    7 years ago

    Thanks, that works.