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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Export Multiple Avalon-mm slave interfaces as one interface

Hi,

I am trying to use the DisplayPort Intel® Stratix 10 FPGA IP Design Example on a Stratix 10 SX device. The design example has a NIOS processor controlling the different Avalon-mm slaves. I have no need for a separate NIOS processor when I have an on board ARM HPS that can do the same thing. I have removed the NIOS processor from the example QSYS project and want to connect the ARM to the Avalon-mm bus in its place.

The issue I am running into is that I cannot figure out how to export the common Avalon-mm bus from the example design as a unified bus. The only option seems to be to export each slave's bus separately. Is there a way to join the buses together and only export a single Avalon-mm bus?

6 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    You shouldn't need to export anything. Connect the H2F bridge (master) to all the FPGA slaves you need to control. You can do this by clicking the appropriate dots in the Connections panel or by right-clicking the master interface, going to the Connections submenu, and selecting the slave interfaces to connect to.

    Or are you saying you need to connect to parts of your design outside of the Platform Designer system?

    #iwork4intel

    • DZuck1's avatar
      DZuck1
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago
      The ARM HPS is in one QSYS design with the H2F bridge exported and the DisplayPort sample design is in another project. Can I connect all of the slaves to an Avalon-mm bridge and export the s0 port from it? I would need to adjust the address range to make sure I can handle all the Avalon-mm slaves.
  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    So you want to create a hierarchical system design. You can make all the connections in Platform Designer without having to make them in your Quartus project by adding the DisplayPort system as a component. The other .qsys should appear in the IP Catalog.

    If you don't want to do this, like you say, add a pipeline bridge to the .qsys file with the ARM processor. Connect the H2F bridge to the slave side and export the master side. That way, if there are any FPGA slaves in the ARM system, you can connect to them as well as export to connect to the other system.

    #iwork4intel

    • DZuck1's avatar
      DZuck1
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago
      I placed an Avalon pipeline bridge to export the unified Avalon bus. This allowed me to connect up to the ARM HPS and keep the addressing in QSYS. Thanks!
  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    feel free to try out sstrell's suggestion.

    Basically the idea is to remove NIOS II connection and convert whole Display Port IP example design as a new custom component in platform designer where you can then hook up to HPS processor.

    Thanks.

    Regards,

    dlim