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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Export Multiple Avalon-mm slave interfaces as one interface

Hi, I am trying to use the DisplayPort Intel® Stratix 10 FPGA IP Design Example on a Stratix 10 SX device. The design example has a NIOS processor controlling the different Avalon-mm slaves. I have ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

So you want to create a hierarchical system design. You can make all the connections in Platform Designer without having to make them in your Quartus project by adding the DisplayPort system as a component. The other .qsys should appear in the IP Catalog.

If you don't want to do this, like you say, add a pipeline bridge to the .qsys file with the ARM processor. Connect the H2F bridge to the slave side and export the master side. That way, if there are any FPGA slaves in the ARM system, you can connect to them as well as export to connect to the other system.

#iwork4intel

  • DZuck1's avatar
    DZuck1
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago
    I placed an Avalon pipeline bridge to export the unified Avalon bus. This allowed me to connect up to the ARM HPS and keep the addressing in QSYS. Thanks!