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Altera_Forum's avatar
Altera_Forum
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8 years ago

Expecting IDENTIFIER in Signals

Hey all, I've googled this problem and it always seems to be a missing semicolon or paren somewhere, but I've looked over my code and I see nothing. I know it's going to be simple and I will fe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

The error is because of the signal declaration.

Provide individual signal declaration like, 

signal d1, d2, d3, d4, d5, t1 : std_logic;
signal a1 : std_logic_vector(7 downto 0); 
signal i1 : std_logic_vector(31 downto 0);

Best Regards

Vikas Jathar

Intel Customer Support – Engineering

(Under Contract to Intel)