example design of AXI Streaming Intel FPGA IP for PCI Express can't pass analyze in quartus

Hi ,

I try to run the example design in Gen 3 1x4, I am getting similar error as you.
BUT, this issue is not observed in Gen3 1x16.

There should be an error when generating/compile if it is not a supported ED.
If referring to AXI Streaming Intel® FPGA IP for PCI Express* User Guide under 3.4. About the AXI Streaming Intel® FPGA IP for PCI Express Design Examples

Obviously, Gen 3 1x4 is not in the option, hence the compilation fail is expected.
If your project requirement is not strict to gen3 1x4, I suggest you to consider other available option.

Hope that answered your question, let me know if there is any further clarification is needed.

Regards,

Wincent_Altera

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