New Contributor
Regular ContributorHi ,
I try to run the example design in Gen 3 1x4, I am getting similar error as you.
BUT, this issue is not observed in Gen3 1x16.
There should be an error when generating/compile if it is not a supported ED.
If referring to AXI Streaming Intel® FPGA IP for PCI Express* User Guide under 3.4. About the AXI Streaming Intel® FPGA IP for PCI Express Design Examples
Obviously, Gen 3 1x4 is not in the option, hence the compilation fail is expected.
If your project requirement is not strict to gen3 1x4, I suggest you to consider other available option.
Hope that answered your question, let me know if there is any further clarification is needed.
Regards,
Wincent_Altera
p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.
New ContributorThank you, Wincent. The device I am using is:AGIB041R31B1I2VC. I generated a example design with gen3 1x16 . Having passed the analysis & synthesis, but unable to pass the jitter, is it necessary to reallocate clock and data pins ?
Regular ContributorHi Geats,
I am able to compile 100 % on Gen3 1x16 in Agilex F-series device.
For your device, You may need to do the pin placement accordingly based on your device OPN.
Because our design's example pin placement is only targeted F-series devkit
Detail about the pin placement you may refer to
Or you may refer to the design .qar in the attachment (for F-series) under .qsf file
You may re-use more then 60-80 % of the pin information.
Regards,
Wincent_Altera
p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.
New ContributorWith the example design of F-series devkit based on your suggestion has passed the compilation. Thank you, Wincent
