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I include SDRAM controller in my system. To make use of the SDRAM I need to know how many clks after sending rd_n until the Data arrives.
process (iCLK,iRESET_n) variable wr_end : std_logic := '0'; begin if iRESET_n = '0' then wr_end := '0'; elsif iCLK'event and iCLK = '1' and wr_end = '0' then wr_end := '1'; az_rd_n_to_sdr <= not(rd_en); az_wr_n_to_sdr <= wr_en; oDATA <= "00000000"; -- "0x00" elsif iCLK'event and iCLK = '1' and wr_end = '1' then az_rd_n_to_sdr <= rd_en; az_wr_n_to_sdr <= not(wr_en); oDATA <= tDATA_to_oDATA; -- the initial value is "0xCC" end if; end process; I can read oDATA out, if the series look like follows: 00CCCCCCFF I can decide that it needs 3 clks. But there is error I can't deal with Error (10483): VHDL error at input_user_logic.vhd(280): can't infer register for signal "az_rd_n_to_sdr" because signal does not hold its value outside clock edge Error (10483): VHDL error at input_user_logic.vhd(280): can't infer register for signal "az_wr_n_to_sdr" because signal does not hold its value outside clock edge Error (10483): VHDL error at input_user_logic.vhd(280): can't infer register for signal "oDATA[7]" because signal does not hold its value outside clock edge Error (10483): VHDL error at input_user_logic.vhd(280): can't infer register for signal "oDATA[6]" because signal does not hold its value outside clock edge Error (10483): VHDL error at input_user_logic.vhd(280): can't infer register for signal "oDATA[5]" because signal does not hold its value outside clock edge Error (10483): VHDL error at input_user_logic.vhd(280): can't infer register for signal "oDATA[4]" because signal does not hold its value outside clock edge Error (10483): VHDL error at input_user_logic.vhd(280): can't infer register for signal "oDATA[3]" because signal does not hold its value outside clock edge Error (10483): VHDL error at input_user_logic.vhd(280): can't infer register for signal "oDATA[2]" because signal does not hold its value outside clock edge Error (10483): VHDL error at input_user_logic.vhd(280): can't infer register for signal "oDATA[1]" because signal does not hold its value outside clock edge Error (10483): VHDL error at input_user_logic.vhd(280): can't infer register for signal "oDATA[0]" because signal does not hold its value outside clock edge Can somebody help me out?
