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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

errors

I include SDRAM controller in my system. To make use of the SDRAM I need to know how many clks after sending rd_n until the Data arrives. process (iCLK,iRESET_n) variable wr_end : std_lo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

elsif iCLK'event and iCLK = '1' and wr_end = '0' then
...
elsif iCLK'event and iCLK = '1' and wr_end = '1' then

I did not check whether this is related to the errors, but it is not standard coding style to include the wr_end check in the same if condition with the clock edge check. Maybe what you are trying to do with wr_end should be done with an if nested inside the "elsif iCLK'event".