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jkmchow's avatar
jkmchow
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2 years ago
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errors found while generate project in "nios II build tools for eclipse"

I am using Quatus Prime Lite 17.1. In Nios II build tool for eclipse, two files were made, "embed" and "embed_system.bsp", of which the build project was done successfully. However, to build project of "embed" failed with errors as followed:


"#error Your SystemID peripheral must be named exactly "sysid" in your SOPC Builder system. Please check that you have properly constructed your system before compiling this program.
^
inc/system_validation.h:32:6: error: #error Your JTAG UART peripheral must be named exactly "jtag_uart" in your SOPC Builder system. Please check that you have properly constructed your system before compiling this program.
#error Your JTAG UART peripheral must be named exactly "jtag_uart" in your SOPC Builder system. Please check that you have properly constructed your system before compiling this program.
^
make: *** [obj/default/main.o] Error 1

20:43:28 Build Finished (took 2s.537ms)"

In the Platform Designer (SOPC Builder system). These names "sysid" and "jtag_uart" were used as the error messages suggested. What are the problems and the solution?

  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    2 years ago

    Hi,

    Could you try using the Nios II SBT design template, and select the Hello World template. Then, you should regenerate a new BSP to see the mismatch of names come from the new BSP, or you were using the old BSP generated with the wrong name.


    Also, what is the FPGA development kit you are using for your project?


    Hope this helps.


    Thank you.


    Regards.

    Kelly


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  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,

    Could you try using the Nios II SBT design template, and select the Hello World template. Then, you should regenerate a new BSP to see the mismatch of names come from the new BSP, or you were using the old BSP generated with the wrong name.


    Also, what is the FPGA development kit you are using for your project?


    Hope this helps.


    Thank you.


    Regards.

    Kelly


    • jkmchow's avatar
      jkmchow
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hello Kelly,

      I am using DE-10 Lite board.

      Good news: The "Hello World" template was used to generate BSP with sysid changed to sysid_qsys, everything worked perfectly without any errors. The elf file was generated and run paired with the hardware design, things went smoothly. The conclusion is that there is something wrong with the given files.

      Thank you for your suggestions and support.

      Joseph

  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


    Thank you.

    Regards,

    Kelly Jialin, GOH