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PAA
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1 year ago

Error(21961): Input port OE of a "13_TRUE_DIFF_SIGNALING" I/O output buffer <path> is not supported

Hi, I am attempting to implement differential bi-directional IO on the HSIO bank with true differential voltage, using the GPIO Intel FPGA IP for Agilex 5 device A5ED065BB32AE6SR0. However, I ...
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PAA
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1 year ago

Thanks.
The only concern which I need to verify on my side is to see if the Voltage swing for the 1.2V SSTL is compatible > Vdiff In(min) on the other side receiver.
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