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PAA
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1 year ago

Error(21961): Input port OE of a "13_TRUE_DIFF_SIGNALING" I/O output buffer <path> is not supported

Hi, I am attempting to implement differential bi-directional IO on the HSIO bank with true differential voltage, using the GPIO Intel FPGA IP for Agilex 5 device A5ED065BB32AE6SR0. However, I ...
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PAA
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1 year ago

Thanks for a quick reply. I had already checked that the 1.2 SSTL works.
The problem is that there is no 1.3V SSTL IO standard to select from the Quartus drop down list under Assignment Editor.
So, as a work around, could you confirm if it would be acceptable to configure the IO to 1.2 SSTL but run it at 1.3V ?
OR could there be any potential issues for damaging the IOs if we configure it at 1.2V, but connect the IO bank to 1.3V ?
We plan to share the same IO bank with CSI Tx signals with mipi-dphy, with 'DPHY' as IO standard.