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Altera_Forum's avatar
Altera_Forum
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12 years ago

Error with VHDL compilation

Hello, I tried for an hour to solve this problem...lets see if u can help me!

here is the code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

library std;

use std.standard.all;

entity Calculador is

port( a : in std_logic_vector (3 downto 0);

b : in std_logic_vector (3 downto 0);

Selop : in std_logic_vector (1 downto 0);

z1 : out std_logic_vector (3 downto 0);

z2 : out std_logic_vector (3 downto 0));

end Calculador;

architecture a of Calculador is

begin

case Selop is

when "00" =>

z1 <= a;

z2 <= b;

when "01" =>

z1 <= a;

z2 <= a;

when "10" =>

z1 <= b;

z2 <= b;

when "11" =>

z1 <= a;

z2 <= b;

end case;

end a;

and it gives me this error: Error (10500): VHDL syntax error at opc.vhd(RED LINES) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement

and this one: Error (10500): VHDL syntax error at opc.vhd(BLUE LINES) near text "case"; expecting ";", or an identifier ("case" is a reserved keyword), or "architecture"

What am I doing wrong?

Thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Ok!, But i think i don't need a process...i putted it cause i saw in a thread....

    And if i put:

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.numeric_std.all;

    use ieee.std_logic_unsigned.all;

    library std;

    use std.standard.all;

    entity Calculador is

    port( a : in std_logic_vector (3 downto 0);

    b : in std_logic_vector (3 downto 0);

    Selop : in std_logic_vector (1 downto 0);

    z1 : out std_logic_vector (3 downto 0);

    z2 : out std_logic_vector (3 downto 0));

    end Calculador;

    architecture a of Calculador is

    begin

    with Selop select

    z1 <= a when "00",

    a when "01",

    b when "10",

    a when "11";

    z2 <= b when "00";----->this line

    a when "01";------>this line

    b when "10";------>this line

    b when "11";

    end a;

    I get the error: Error (10500): VHDL syntax error at opc.vhd(THESE LINES) near text ","; expecting ";"

    Do i need a process? or i'm doing wrong other things?

    Thank you to answer so fast
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    you can only assing 1 signal with a select. So you either need another "with Selop select" for z2, or assign it like:

    z2 <= b when Selop = "00" else a when selop = "01" --etc
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    first case is a sequential statement and therefore will not get this working you need to add a process in your code

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.numeric_std.all;

    use ieee.std_logic_unsigned.all;

    library std;

    use std.standard.all;

    entity Calculador is

    port( a : in std_logic_vector (3 downto 0);

    b : in std_logic_vector (3 downto 0);

    Selop : in std_logic_vector (1 downto 0);

    z1 : out std_logic_vector (3 downto 0);

    z2 : out std_logic_vector (3 downto 0));

    end Calculador;

    architecture a of Calculador is

    begin

    process (Selop)

    begin

    case Selop is

    when "00" =>

    z1 <= a;

    z2 <= b;

    when "01" =>

    z1 <= a;

    z2 <= a;

    when "10" =>

    z1 <= b;

    z2 <= b;

    when "11" =>

    z1 <= a;

    z2 <= b;

    end case;

    end process;

    end a;