Error with VHDL compilation

Ok!, But i think i don't need a process...i putted it cause i saw in a thread....

And if i put:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

library std;

use std.standard.all;

entity Calculador is

port( a : in std_logic_vector (3 downto 0);

b : in std_logic_vector (3 downto 0);

Selop : in std_logic_vector (1 downto 0);

z1 : out std_logic_vector (3 downto 0);

z2 : out std_logic_vector (3 downto 0));

end Calculador;

architecture a of Calculador is

begin

with Selop select

z1 <= a when "00",

a when "01",

b when "10",

a when "11";

z2 <= b when "00";----->this line

a when "01";------>this line

b when "10";------>this line

b when "11";

end a;

I get the error: Error (10500): VHDL syntax error at opc.vhd(THESE LINES) near text ","; expecting ";"

Do i need a process? or i'm doing wrong other things?

Thank you to answer so fast