Error with VHDL compilation

first case is a sequential statement and therefore will not get this working you need to add a process in your code

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

library std;

use std.standard.all;

entity Calculador is

port( a : in std_logic_vector (3 downto 0);

b : in std_logic_vector (3 downto 0);

Selop : in std_logic_vector (1 downto 0);

z1 : out std_logic_vector (3 downto 0);

z2 : out std_logic_vector (3 downto 0));

end Calculador;

architecture a of Calculador is

begin

process (Selop)

begin

case Selop is

when "00" =>

z1 <= a;

z2 <= b;

when "01" =>

z1 <= a;

z2 <= a;

when "10" =>

z1 <= b;

z2 <= b;

when "11" =>

z1 <= a;

z2 <= b;

end case;

end process;

end a;