Forum Discussion
JPrig
Occasional Contributor
Occasional ContributorError while simulating Cyclone 10 GX PLL
Hi, I want to simulate a simple test project for Cyclone 10 GX. My tool is Aldec Riviera PRO. I instantiate a PLL (IOPLL Intel FPGA IP) and a FIFO in Quartus 24.3 PRO. In Quartus the project compil...
RichardT_altera
Super Contributor
Super ContributorNoted Julia.
May I know the estimate time when you will try it out?
Regards,
Richard Tan
JPrigOccasional Contributor
Occasional ContributorHi Richard,
As it looks right now, I will just bypass the whole PLL for the rest of the project. I will not spend time on debugging this problem.
Best regards,
Julia
