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JPrig's avatar
JPrig
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Error while simulating Cyclone 10 GX PLL

Hi, I want to simulate a simple test project for Cyclone 10 GX. My tool is Aldec Riviera PRO. I instantiate a PLL (IOPLL Intel FPGA IP) and a FIFO in Quartus 24.3 PRO. In Quartus the project compil...
Simulation
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Dropping a note to ask if my last reply was helpful to you.

Do you able to resolve the issue?


Best Regards,

Richard Tan


  • JPrig's avatar
    JPrig
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi Richard,

    thanks for the suggestion. I proceeded with overriding/forcing the PLL outputs from my testbench for now, as I am on a critical project line with this. I'll need to try out Verilog at a later point.

    Best regards,

    Julia