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JPrig's avatar
JPrig
Icon for New Contributor rankNew Contributor
1 year ago

Error while simulating Cyclone 10 GX PLL

Hi, I want to simulate a simple test project for Cyclone 10 GX. My tool is Aldec Riviera PRO. I instantiate a PLL (IOPLL Intel FPGA IP) and a FIFO in Quartus 24.3 PRO. In Quartus the project compil...
Simulation
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

The ELAB2_0093 Fatal Error seem to indicate that a mismatch in your design that arises because a defparam statement is trying to modify a parameter (reference_clock_frequency) in a module that is not defined in Verilog.

Some IP cores require the Verilog variant, as the VHDL version is not supported for certain IPs.


Could you try using the Verilog variant instead and check if the error is resolved?


Regards,

Richard Tan