Forum Discussion
JPrig
Occasional Contributor
Occasional ContributorError while simulating Cyclone 10 GX PLL
Hi, I want to simulate a simple test project for Cyclone 10 GX. My tool is Aldec Riviera PRO. I instantiate a PLL (IOPLL Intel FPGA IP) and a FIFO in Quartus 24.3 PRO. In Quartus the project compil...
RichardT_altera
Super Contributor
Super ContributorThe ELAB2_0093 Fatal Error seem to indicate that a mismatch in your design that arises because a defparam statement is trying to modify a parameter (reference_clock_frequency) in a module that is not defined in Verilog.
Some IP cores require the Verilog variant, as the VHDL version is not supported for certain IPs.
Could you try using the Verilog variant instead and check if the error is resolved?
Regards,
Richard Tan
