Forum Discussion
JPrig
Occasional Contributor
Occasional ContributorError while simulating Cyclone 10 GX PLL
Hi, I want to simulate a simple test project for Cyclone 10 GX. My tool is Aldec Riviera PRO. I instantiate a PLL (IOPLL Intel FPGA IP) and a FIFO in Quartus 24.3 PRO. In Quartus the project compil...
sstrell
Super Contributor
Super ContributorAre you trying to use Verilog or VHDL for this and does your simulation tool support mixed-language designs?
It looks like you generated the PLL as Verilog but you're trying to compile in the sim tool as VHDL (or vice versa).
JPrigOccasional Contributor
Occasional ContributorI use VHDL for my custom code and I generate all IPs as VHDL, picture attached.
Our Riviera PRO licenses support both VHDL and Verilog, picture attached.
