Forum Discussion

JPrig's avatar
JPrig
Icon for New Contributor rankNew Contributor
1 year ago

Error while simulating Cyclone 10 GX PLL

Hi, I want to simulate a simple test project for Cyclone 10 GX. My tool is Aldec Riviera PRO. I instantiate a PLL (IOPLL Intel FPGA IP) and a FIFO in Quartus 24.3 PRO. In Quartus the project compil...
Simulation
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

Are you trying to use Verilog or VHDL for this and does your simulation tool support mixed-language designs?

It looks like you generated the PLL as Verilog but you're trying to compile in the sim tool as VHDL (or vice versa).

JPrig's avatar
JPrig
Icon for New Contributor rankNew Contributor
1 year ago

I use VHDL for my custom code and I generate all IPs as VHDL, picture attached.

Our Riviera PRO licenses support both VHDL and Verilog, picture attached.