error while generating hdl in platform designer.

Question

Greetings all!

I'm trying to do a project using nios 2 processor. I have already created a qsys file in that i have included my CSR hdl file using component editor. I'm getting the following error while generating the testbench and hdl files. I can't figure out how to solve it.

Error: CSR_0: CSR does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis.
Error: Generation stopped, 11 or more modules remaining
Error: qsys-generate failed with exit code 1: 2 Errors, 0 Warnings

After that I created the application make files using nios 2 sbt while running the simulation in modelsim  I'm getting the following errors.
Instantiation of 'nios_CSR_0' failed. The design unit was not found.

Instantiation of 'altera_avalon_i2c' failed. The design unit was not found.

Instantiation of 'nios_NIOS_CONSOLE_UART' failed. The design unit was not found.

Does anybody have any suggestions? I really appreciate the help.

Thank you.

Platform Designer: Component Editor

sstrell · Answer

When you created your component in Component Editor, on the Files tab, did you put files in the Verilog simulation section?  It can be the same files as in the synthesis section (there's even a button to copy them over), but if you want to simulate your custom component through a testbench system, you need to indicate which design files to use for simulation separate from synthesis.

shengn_altera · Answer

Hi,Let me know if you have any further concern.Best Regards,Shengp/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.

rishivanthishankaran · Answer

Yes, I have put those testbench files in the simulation section though I'm getting the same error again.

rishivanthishankaran · Answer

Hi,
  could you please tell me how to include the CSR hdl file in nios 2 processor . I have included it using component editor though I'm getting error.

shengn_altera · Answer

Hi,Check the links below:https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/specify-files-for-simulation-in-the.htmlhttps://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/specify-files-for-simulation-in-the.htmlNote: The order that you add files to the fileset determines the order of compilation. For VHDL filesets with VHDL files, you must add the files bottom-up, adding the top-level file last.Best Regards,Shengp/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.

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error while generating hdl in platform designer.

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