Forum Discussion
rishivanthishankaran
New Contributor
New Contributorerror while generating hdl in platform designer.
Greetings all!
I'm trying to do a project using nios 2 processor. I have already created a qsys file in that i have included my CSR hdl file using component editor. I'm getting the following erro...
sstrell
Super Contributor
Super ContributorWhen you created your component in Component Editor, on the Files tab, did you put files in the Verilog simulation section? It can be the same files as in the synthesis section (there's even a button to copy them over), but if you want to simulate your custom component through a testbench system, you need to indicate which design files to use for simulation separate from synthesis.
rishivanthishankaranYes, I have put those testbench files in the simulation section though I'm getting the same error again.
