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rishivanthishankaran's avatar
rishivanthishankaran
Icon for New Contributor rankNew Contributor
3 years ago

error while generating hdl in platform designer.

Greetings all! I'm trying to do a project using nios 2 processor. I have already created a qsys file in that i have included my CSR hdl file using component editor. I'm getting the following erro...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Check the links below:

https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/specify-files-for-simulation-in-the.html

https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/specify-files-for-simulation-in-the.html

Note: The order that you add files to the fileset determines the order of compilation. For VHDL filesets with VHDL files, you must add the files bottom-up, adding the top-level file last.


Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.