--- Quote Start ---
As FvM indicated this error message is caused by the fact that no VHDL entity is found with the name of the "
top level entity". It is not enough to name your VHDL file with the name of the top entity. The top entity itself of your VHDL description should have this name.
e.g. In the example below TOP is the "Top Level Entity" and has been declare d like that (see @pletz) file TOP.vhd
entity TOP is
port (
...
);
end TOP;
architecture my_design of TOP is
begin
...
end my_design;
--- Quote End ---
Hey man, I should say thank you. I was suffering with the same problem and the solution proposed by you solved it.
Thank you so much
have a good day
Honored Contributor
