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Altera_Forum
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18 years ago

Error: top level design entity " " is undefined

we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity " file name" is undefined. We are even taking care of the case se...
Altera_Forum's avatar
Altera_Forum
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18 years ago

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The said error message means, that no entity with the said top-level name can be found in any of the design files, the error can clearly be distinguished from file not found.

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Hi FvM,

when the top-level file isn't in the file list, you don't get any message about a missing file.

Did you get a warning like this during Analysis and Elaboration ?

Warning: Can't analyze file -- file C:/altera/quartus80sp1/qdesigns/vhdl_verilog_tutorial/addersubtractor.vhd is missing