Error: top level design entity " " is undefined

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we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity " file name" is undefined.

We are even taking care of the case sensitivity.

Our file name, new created project name and entity name in the code are all same.

Plz help us regarding this.

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Hi,

did you set the toplevel correctly ? You can check that in Quartus :

Assignments -> Device -> General

Look to the field "Toplevel entity". If this is not your toplevel, write it down here.

Kind regards