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New ContributorError: loop with non-constant loop condition must terminate within 250 iterations
You may try the following solution:
Description
This error may appear in the Quartus® II software when synthesis iterates through a loop in Verilog HDL for more than the synthesis loop limit. This limit prevents synthesis from potentially running into an infinite loop. By default, this loop limit is set to 250 iterations.
Resolution
To work around this error, the loop limit can be set using the VERILOG_NON_CONSTANT_LOOP_LIMIT option in the Quartus II Settings File (.qsf). For example:
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 300
Super ContributorHi,
I see that the error is generated when you are compiling the testbench code in Quartus. This makes no sense, testbench must be compiled in simulator, e.g. Modelsim Altera Starter Edition shipped with Quartus 18.
New Contributoryes I know but still it is throwing this error
