Forum Discussion
New ContributorError: loop with non-constant loop condition must terminate within 250 iterations
You may try the following solution:
Description
This error may appear in the Quartus® II software when synthesis iterates through a loop in Verilog HDL for more than the synthesis loop limit. This limit prevents synthesis from potentially running into an infinite loop. By default, this loop limit is set to 250 iterations.
Resolution
To work around this error, the loop limit can be set using the VERILOG_NON_CONSTANT_LOOP_LIMIT option in the Quartus II Settings File (.qsf). For example:
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 300
Super ContributorDoes the error point to a line number? What tool does this happen in?
There are no loops here with fixed iteration unless it's something in the PulseCounter.
New ContributorPoints to line 18 i.e. (#`HALF_CLOCK tb_clk = ~tb_clk;)
Tool: Intel quartus prime 18.1 when I am writing a test bench
