Error in Timing Simulation Display

Gate-level timing simulation is supported only for the Arria II GX/GZ, Cyclone IV, MAX II, MAX V, and Stratix IV device families.

Unfortunately, the gate-level timing simulation is Not supported for Cyclone V device.

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683080/22-1/simulation-levels.html

We recommend that you use Timing Analyzer tool available in Quartus, to verify the timing performance of a design.

You may checkout the User Guide below on how-to use the Timing Analyzer:

https://www.intel.com/content/www/us/en/programmable/documentation/ony1529966370740.html

Best Regards,

Richard Tan

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