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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

error in compling verilog module

I write this module and when compile it get error "Error (12153): Can't elaborate top-level user hierarchy"

file attached.

can any one help me?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    Just wonder if you have tried to add your file to the Quartus II and then set this file as top level entity? It seems like Quartus II could not identify the top level file during compilation.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi

    I set this file as top entity but still give this error.

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi

    change

    always@(posedge csi_clockreset_clk or csi_clockreset_reset_n)

    to

    always@(posedge csi_clockreset_clk or negedge csi_clockreset_reset_n)

    and correct.