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Altera_Forum
Honored Contributor
Honored Contributorerror in compling verilog module
I write this module and when compile it get error "Error (12153): Can't elaborate top-level user hierarchy" file attached. can any one help me?
Altera_ForumHonored Contributor
Honored ContributorHi
change always@(posedge csi_clockreset_clk or csi_clockreset_reset_n) to always@(posedge csi_clockreset_clk or negedge csi_clockreset_reset_n) and correct.
