Altera_Forum
Honored Contributor
9 years agoError during QSYS generation
I'm getting strange error during generation of system with DDR2 controller
Error: GenerateSim: Could not move C:\Users\WAT\AppData\Local\Temp\alt7310_6655338575060564170.dir\0001_iptb_gen\DRAMsystem_altmemddr_0_mem_model.v to C:\Users\WAT\AppData\Local\Temp\alt7310_6655338575060564170.dir\0001_iptb_gen\testbench\DRAMsystem_altmemddr_0_mem_model.v system is minimal, it has only clock bridge and entrance from external bus. I generate only system, no simulation files. I can see some files being generated in the said folder, but the compilation stops on this file. Problem persists in Q16.1 and Q17 Earlier versions of system (more complicated) with this IPcore were generated successfully in Q13 I guess. (i changed computer and don't have all archives now) Can You generate system with DDR2 in Your newest quartusses?