Altera_Forum
Honored Contributor
Honored ContributorError: Can't simulate mismatched node types
Good day, I design ALU (arithmetic and logic unit) in the language of Verilog HDL. When I try to simulate the circuit though I get these errors:
--- Quote Start --- Warning: Wrong node type for node "result[0]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Warning: Wrong node type for node "result[1]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Warning: Wrong node type for node "result[2]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Warning: Wrong node type for node "result[3]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Warning: Wrong node type for node "result[4]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Warning: Wrong node type for node "result[5]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Warning: Wrong node type for node "result[6]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Warning: Wrong node type for node "result[7]" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Warning: Wrong node type for node "flagZ" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Warning: Wrong node type for node "flagO" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Warning: Wrong node type for node "flagN" in vector source file. Design node is of type Output, but signal in vector source file is of type Input. Error: Can't simulate mismatched node types Error: Quartus II 64-Bit Simulator was unsuccessful. 11 errors, 11 warnings --- Quote End --- What am I doing wrong here? P.S. I live in Russia, and does not know very well English. Forgive my ignorance.
