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Altera_Forum
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12 years ago

Error: Can't simulate mismatched node types

Good day, I design ALU (arithmetic and logic unit) in the language of Verilog HDL. When I try to simulate the circuit though I get these errors: --- Quote Start --- Warning: Wrong node t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I don't think so there is any problem in your source code.I think problem is in your test bench. So please provide your test bench.

I found one typo error in your source line 271.It should be z = (res == 0) ? 1 : 0 instead of z = (res=0) ? 1 : 0.