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Altera_Forum's avatar
Altera_Forum
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17 years ago

Error: Can't place pin mem_dq[2] to location R8

Hi,

I build a project of cycloneIII including CFI,SSRAM,DDR SDRAM,PIO,JTAG and PLL.

But when I fit it there is the error as show below:

Error: Can't place pin mem_dq[2] to location R8.

Error: Too many output and bidirectional pins in I/O bank 3 assigned near VREF pin T6 (VREFGROUP_B3_N0) on device EP3C25F324C8 -- no more than 9 output and bidirectional pins allowed near the VREF pin when voltage referenced pins are driving in, but there are potentially 10 pins driving out

Info: Pin mem_addr[1] of type output at location U5 uses SSTL-2 Class I I/O standard

Info: Pin mem_dqs[1] of type output at location T8 uses SSTL-2 Class I I/O standard

Info: Pin mem_addr[4] of type output at location P8 uses SSTL-2 Class I I/O standard

Info: Pin mem_addr[2] of type output at location U7 uses SSTL-2 Class I I/O standard

Info: Pin mem_addr[3] of type output at location U8 uses SSTL-2 Class I I/O standard

How to get over it? I try many ways.

But if I build a project no CFI and SSRAM, it fit successful.

My board is CycloneIII starter board and pin assigned as reference.

Thank you.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    As far as I see, the cycloneiii_3c25_start_niosii_standard is using the same resources and compiles without errors. Did you import the DDR RAM design *.tcl files, particularly the pin assignments, including the output-enable-group assignments for bidirectional DDR pins?

    If all necessary settings are in effect and the error would be due to an incompatible pin assignement of the Evalboard, some outputs in the B3_N0 Vref group may be declared static by assigning a ToggleRate of 0 MHz to them. They are ignored for I/O pin distance rules then.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    As far as I see, the cycloneiii_3c25_start_niosii_standard is using the same resources and compiles without errors. Did you import the DDR RAM design *.tcl files, particularly the pin assignments, including the output-enable-group assignments for bidirectional DDR pins?

    If all necessary settings are in effect and the error would be due to an incompatible pin assignement of the Evalboard, some outputs in the B3_N0 Vref group may be declared static by assigning a ToggleRate of 0 MHz to them. They are ignored for I/O pin distance rules then.

    --- Quote End ---

    the error is occured yet.

    the DDR RAM design *.tcl files have imported. and the direction of pins are right.

    I didn't understand

    --- Quote Start ---

    some outputs in the B3_N0 Vref group may be declared static by assigning a ToggleRate of 0 MHz to them

    --- Quote End ---

    and how to correct it.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    - Did you check the design differences to cycloneIII_3c25_start_niosII_standard?

    - Search for "toggle rate 0MHz" in Altera Knowledgebase.