Error: archiver reported: Internal Error: Sub-system: QIS, File: /quartus/synth/qis/qis_name_processor.cpp, Line: 779

I was trying to synthesize a mixed VHDL Verilog design with Quartus 19.4 but I encountered this error: "Error: archiver reported: Internal Error: Sub-system: QIS, File: /quartus/synth/qis/qis_name_p...