Forum Discussion
Altera_Forum
Honored Contributor
8 years agoI do not see any useful information in the log as to why the compilation is failing. If this happens when the design gets too large, you are either running out of some resource on the FPGA, or you are running out of memory on your compilation machine. Check your top.fit.summary file to see if any of the resource utilization numbers is over 100%, or far too low, the latter showing overflowing of the resource utilization numbers.