Error (204005): Can't generate output netlist file

Hi everyone!

I'm trying to simulate a exemple provided by analog devices in modelsim, using the nativelink for that. The dut and testbench files are provided too, so it's just run the code to work. All simulation is successfully compiled, but 2 errors persists.

Are they:

Error (204005): Can't generate output netlist file C:/intelFPGA_lite/19.1/modelsim_ase/win32aloem/CED1_modelsim.xrf -- output netlist files are read-only

Error (204005): Can't generate output netlist file C:/intelFPGA_lite/19.1/modelsim_ase/win32aloem/CED1.vo -- output netlist files are read-only

The example code it's about the AD7760. Has someone here had the same error?