Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27

Hello everybody,

I am using the Max10 chip with the Quartus Prime 17.1. I am building a SPI interface for ADC. The input pin for my on-board quartz oscillator is the pin 27 (bank 2). I have designated pin 26 (bank 2) for a SPI clock output. When I try to compile the design I get the following error:

++++++++++++++++++++++ Start Error Message ++++++++++++++++++

Error (18496): The Output SCLK in pin location 26 (pad_711) is too close to PLL clock input pin (clk_in) in pin location 27 (pad_0)

Error (171000): Can't fit design in device

Error: Quartus Prime Fitter was unsuccessful. 2 errors, 4 warnings

Error: Peak virtual memory: 909 megabytes

Error: Processing ended: Thu Apr 19 18:28:02 2018

Error: Elapsed time: 00:00:05

Error: Total CPU time (on all processors): 00:00:03

Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 8 warnings

+++++++++++++++++++++++ End Error Message ++++++++++++++++++

I have also tried fitting the design by moving the SPI clock output to other CLK pins (28,29) in the same bank, and I get the same error message. If I use pins which are not CLK pins (30,32,33) in the same bank or any other pin in different bank the design can compile succesfully.

Does anyone know why is Quartus giving this error?

Thanks in advance and Cheers,

Milos

14 Replies

Show More
  • TSute's avatar
    TSute
    Icon for New Contributor rankNew Contributor
    7 years ago

    ​I have actually the same problem. But I intentionlly want to drive the neighbour pin constant low. The pins are connected to GND on the PCB. This is the concept of Virtual GND Pins, which support the clock Input and protect it from other neighbours. How can I drive the pin low without this error message from the fitter?

  • CKPope's avatar
    CKPope
    Icon for New Contributor rankNew Contributor
    3 years ago

    I am tasked with getting our Quartus tools running for one of our university course offerings. The development board that is used was designed in 2015 and the Quartus Tools (Altera Quartus Prime v15.1) were used as part of the pin assignments and fitting etc. It has served us very well.

    We have the board running with the an LED output driving pin 28 with no issues. But our Altera Quartus v15.1 tools have expired. So we are looking at migrating to the newer tools. But we need to override this Fitter problem.

    Using newer versions of the Quartus tools (v16.1 and later), the same fitting error described above became evident.

    Is there a tcl command that can be used to ignore this error?

  • 2reSolve's avatar
    2reSolve
    Icon for New Contributor rankNew Contributor
    10 months ago

    I also need urgent help to override this fitter Error (18496): The Output TLK_TX[1] in pin location 28 (pad_1628) is too close to PLL clock input pin (CLK_50M) in pin location 29 (pad_1)

    Our FPGA and hardware design was also back in 2015 using Quartus v15.0.2.153

    1. Have anyone found a work-around on this problem?

    2. Can Intel help come up with a solution to this problem?