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Altera_Forum's avatar
Altera_Forum
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8 years ago

Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27

Hello everybody, I am using the Max10 chip with the Quartus Prime 17.1. I am building a SPI interface for ADC. The input pin for my on-board quartz oscillator is the pin 27 (bank 2). I have des...
TSute's avatar
TSute
Icon for New Contributor rankNew Contributor
6 years ago

​I have actually the same problem. But I intentionlly want to drive the neighbour pin constant low. The pins are connected to GND on the PCB. This is the concept of Virtual GND Pins, which support the clock Input and protect it from other neighbours. How can I drive the pin low without this error message from the fitter?