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Altera_Forum's avatar
Altera_Forum
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8 years ago

Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27

Hello everybody, I am using the Max10 chip with the Quartus Prime 17.1. I am building a SPI interface for ADC. The input pin for my on-board quartz oscillator is the pin 27 (bank 2). I have des...
2reSolve's avatar
2reSolve
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1 year ago

I also need urgent help to override this fitter Error (18496): The Output TLK_TX[1] in pin location 28 (pad_1628) is too close to PLL clock input pin (CLK_50M) in pin location 29 (pad_1)

Our FPGA and hardware design was also back in 2015 using Quartus v15.0.2.153

1. Have anyone found a work-around on this problem?

2. Can Intel help come up with a solution to this problem?