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Altera_Forum's avatar
Altera_Forum
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8 years ago

Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27

Hello everybody, I am using the Max10 chip with the Quartus Prime 17.1. I am building a SPI interface for ADC. The input pin for my on-board quartz oscillator is the pin 27 (bank 2). I have des...
TBarn2's avatar
TBarn2
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7 years ago

Any response to this ? Doesn't the latest Quartus have some options to disable this error and make it a warning ?

If not can i somhow put in a request to add the ability for Quartus to ignore this error and make it a warning ? We need to use all of the pins available on this chip and have a number of lines that only toggle once at power up or else very infrequently and it seems that the Quatus software should allow us to use the 3 pins next to the clock input lines for output? Or are there serious issues in using these pins ? Alternatively is there some Opensource software we can use instead of Quartus ?