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Altera_Forum's avatar
Altera_Forum
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8 years ago

Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27

Hello everybody, I am using the Max10 chip with the Quartus Prime 17.1. I am building a SPI interface for ADC. The input pin for my on-board quartz oscillator is the pin 27 (bank 2). I have des...
TBarn2's avatar
TBarn2
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7 years ago

Some more on this. If I set our pin wifi_enable (pin 28) which is next the our pin clk_24Mhz (pin 27) to be an input rather than an output the quartus software does not produce any errors or even warnings. Although I realise having an output driven close to the FPGA is likely to produce more noise, I would have thought that the quartus software should at least produce a warning in this case ?

Anyway how can I override the "Error (18496):" for our design as I don't think this is going to cause us any issues and will, at least, allow us to proceed with development on the boards we have ?