Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorError (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27
Hello everybody, I am using the Max10 chip with the Quartus Prime 17.1. I am building a SPI interface for ADC. The input pin for my on-board quartz oscillator is the pin 27 (bank 2). I have des...
Altera_ForumHonored Contributor
Honored Contributorstmilos,
I don't want to sound like your mother, but this demonstrates why you should ALWAYS create a top level design in Quartus and do pin assignments BEFORE committing to hardware.
