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Altera_Forum
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8 years ago

Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27

Hello everybody, I am using the Max10 chip with the Quartus Prime 17.1. I am building a SPI interface for ADC. The input pin for my on-board quartz oscillator is the pin 27 (bank 2). I have des...
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Altera_Forum
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8 years ago

Hello sstrell,

What you said is not correct. The "CLK" pins (26,27,28,29) can also be used as general purpose I/O. I have tried using the internal oscillator of the Max10 to generate the main clock from which the SPI clock is derived, and output SPI clock on the same pin (26). The design compiled and it was running. Also, when I placed the SPI clock output to a "CLK" pin in different bank, the design was able to compile.

There seems to be a problem only when one "CLK" pin is used as an input from on-board oscillator and the other as a clock output, in the same bank.

Cheers,

Milos