Error (18496): The Output SCLK in pin 26 is too close to PLL clock input in pin 27

The MAX10 clock inputs are also useable as general IO, but pin distance rules have to be observed.

You didn't tell why you wanted to use the said pins as SCK output. Technically, you'd either use any suitable IO pin, or in case of very critical timing (unlikely for SPI interface), a dedicated PLL output pin.

If you have already finished a PCB and want to check if the SCK output at pin 26 actually disturbs the input clock, you can disable the fitter check by specifying a TOOGLE_RATE of 0MHz for the pin in the pin planner or assignment editor.