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Altera_Forum
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13 years ago

Error 10500: VHDL Syntax

I am working on a code for a basic vending machine that will give out a product at 75cents

BUt for some reason I dont know how to fix this syntax error


Library ieee;
Use ieee.numeric_std.all;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity Lab06 is
	Port (
				Clock					:IN 	std_logic;
				Reset_n				:IN	std_logic;
				Quarter_in			:IN	std_logic;
				Dime_in				:IN	std_logic;
				Nickel_in			:IN	std_logic;
				Pennny_in			:IN 	std_logic;
				Coin_Return			:IN	std_logic);
End Lab06;
Architecture Behavior Of Lab06 is
Signal int_counter:	std_logic_vector(25 downto 0);
Constant MAXVALUE:	std_logic_vector(25 downto 0):= "10111110101111000010000000"; --One Second Count
-------------------------------------------------------------------------------------------------
Type State_type is (wait1, penny, dime, nickel, quarter, enough, excess, vend, change);
Signal current_state,next_state: state_type;
Signal Money:								std_logic_vector(6 downto 0);
Signal Red_Bull:							std_logic;
Signal Change_Back:						std_logic;
Begin
Counter_Clock:Process (clock, reset_n)
	Begin
	If reset_n = '0' Then
		Int_counter <= (Others => '0');
	Elsif (rising_edge(clock)) Then
		If int_counter = MAXVALUE Then
			int_counter <= (Others => '0');
		Else 
			int_counter <= int_counter + '1';
		End If;
	End If;
End Process;
Sync:Process (clock, reset_n)
	Begin
		If (reset_n = '0')then
			Current_state <= Wait1;--Wait1 is the default state_type
		Elsif(rising_edge(clock))Then
			If (int_counter = MAXVALUE)Then
				Current_state <=next_state;-- Advance the state(Red Bull)machine
			End If;
		End If;
	End Process;
Comb:Process(int_counter,current_state, Quarter_in, Dime_in, Nickel_in, Pennny_in, money, Coin_Return)
	Begin
	If (int_counter = MAXVALUE) Then
		Case(current_state)is
				When wait1=>
					If (money = "0000000")Then -- No money in vending machine
						next_state <= Wait1;
					If (Quarter_in = '1')Then -- Money is inserted
						next_state <= Quarter;
					If (Dime_in = '1')Then
						next_state <= Dime;
					If (Nickel_in = '1')Then
						next_state <= Nickel;
					If (Pennny_in = '1')Then
						next_state <= Penny;
					If (money >= "1001011")Then
						next_state <=  Enough;
					If(Coin_Return = '1')Then
						next_state <= Change;
						Else
							next_state <=Wait1;
					End If;
-----------------------------------------------------------------  After Quarter Inserted, next step
				When Quarter =>
					Next_state <= Wait1;
-----------------------------------------------------------------  After Dime Inserted, next step				
				When Dime =>
					Next_state <= Wait1;
-----------------------------------------------------------------  After Nickel Inserted, next step
				When Nickel =>
					Next_state <= Wait1;
-----------------------------------------------------------------  After Penny Inserted, next step
				When Penny =>
					Next_state <= Wait1;
				
				When Enough =>
					If (money >= "1001011")Then
						Next_state <= Excess;
					Else
						Next_state <= vend;
					End If;
				When Excess =>
					Next_state <= vend;
				When vend =>
					Next_state <= Wait1;
				When Change =>
					Next_state <= Wait1;
				When OTHERS =>
					next_state <= Wait1;					
				End Case;
			End If;
		End Process;
-----------------------------------------------------------------  Money calculation 
Money_Calc:Process(Current_state, money)
	Begin
		Case (current_state) is
			When wait1 =>
				Money <= Money;
			When Quarter =>
				Money <= Money + "0011001";
			When Dime =>
				Money <= Money + "0001010";
			When Nickel =>
				Money <= Money + "0000101";
			When Penny =>
				Money <= Money + "0000001";
			When Enough =>
				Money <= money;
			When Excess =>
				Money <= Money;
			When vend =>
				Money <= Money - "1001011";
			When change =>
				Money <= "0000000";
			When OTHERS =>
				Money <= Money;
		End Case;
	End Process;
End Behavior;

The errors I am getting are

Info: *******************************************************************

Info: Running Quartus II 32-bit Analysis & Synthesis

Info: Version 12.0 Build 178 05/31/2012 SJ Full Version

Info: Processing started: Wed Oct 31 15:32:29 2012

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab06 -c Lab06

Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

Info (12021): Found 2 design units, including 1 entities, in source file hex_display.vhd

Info (12022): Found design unit 1: Hex_Display-Structure

Info (12023): Found entity 1: Hex_Display

Error (10500): VHDL syntax error at Lab06.vhd(108) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(111) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(114) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(117) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(120) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(126) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(128) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(130) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(132) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(134) near text "Case"; expecting "if"

Error (10500): VHDL syntax error at Lab06.vhd(136) near text "Process"; expecting "if"

Error (10500): VHDL syntax error at Lab06.vhd(139) near text "Begin"; expecting ":=", or "<="

Error (10500): VHDL syntax error at Lab06.vhd(162) near text "Process"; expecting "if"

Info (12021): Found 0 design units, including 0 entities, in source file lab06.vhd

Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 13 errors, 0 warnings

Any assistance would be very helpful.

30 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Error (10500): VHDL syntax error at neural_processor.vhd(356) near text "case"; expecting "if"

    Could be a second version like:

    Error(1): VHDL syntax error in keyword "case" at line xxx, missing a "end case"

    or

    Error(2): VHDL syntax error in keyword "if" at line xxx, missing a "end if"

    Is hard to make that? No, it is not!

    --- Quote End ---

    Syntax errors are the lowest level of possible code faults, and the kind of errors that can be most easily located and fixed. I see two possible reasons why a syntax error of the said kind (expecting "if" instead of "case") might cause headache:

    - you are really new to VHDL

    - it's appearing in a large code block with nested "if" and "case" constructs.

    Your both suggestions are in my view more confusing than the original error message. Error(1) is just inappropriate, error(2) is only halfway correct. The error is a missing "end if", but it's not an "error in keyword if". The compiler is exactly reporting what it sees: It has an open "if" block which must be closed before a (possibly) correct end case.

    --- Quote Start ---

    I remember how i solved this problem and i will tell you:

    I broke about 1500 lines of code in 750. I compiled and chose the bad part.

    I broke again in two parts of 375 and did it again, and again, and again until: "Oh i forgot a semicolon here...". Now tell me: Where is my fault? Have I "poor knowledge of VHDL" like you said just because i forgot a semicolon, or a "end case"? Is It serious?

    --- Quote End ---

    If the actual error is a missing semicolon, the error message would look like

    Error (10500): VHDL syntax error at Range_I.vhd(227) near text "IF";  expecting ";", or an identifier ("if" is a reserved keyword)
    Error (10500): VHDL syntax error at Range_I.vhd(232) near text "CASE";  expecting "if"
    

    Error messages should be always decoded (and fixed) top-down. Either you omitted the first error message, or the case is a bit different.

    The solution description suggests that besides not exactly reading the error message the problem is probably not well structured and indented code.

    I admit that a verbose error message could explain about the open if block and also tell the line number of related unmatched "if". I'm not aware of a VHDL tool doing so. In a well structured and indented text, the actual error location can be quickly found without it.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Take a look in my code, i did specially to show the ERROR of compiler message:

    entity ALTERA_COMPANY is
    port(
    	CUSTOMER_TRYING_HELP_ALTERA: in std_logic; 
    	
    	TIME_OF_CUSTOMERS: in std_logic; 
    	
    	ALTERA_START: in std_logic;
    	
    	ALTERA_SUPPORT_BLAMES_THE_CUSTOMER: out std_logic;
    	
    	ALTERA_CLOSE_THE_DOORS: out std_logic
    	
    );
    end ALTERA_COMPANY;
    architecture very_bad_behavior of ALTERA_COMPANY is		 	  
    	   
    	-- Contador de elementos a serem processados
    	signal Altera_Customers: std_logic_vector(3 downto 0);
    	   
    begin
           	
           	process(CUSTOMER_TRYING_HELP_ALTERA,TIME_OF_CUSTOMERS)
           	begin			
    			
    			
    			if(TIME_OF_CUSTOMERS='1' and TIME_OF_CUSTOMERS'event) then
    			
    				case ALTERA_START is
    			
    					when '0' =>
    					
    						if(CUSTOMER_TRYING_HELP_ALTERA = '1' and Altera_Customers /= "0100") then
    			
    							Altera_Customers <= Altera_Customers - 1;
    						
    						end if;
    					
    					when '1' =>
    				
    						Altera_Customers <= "1111";
    				
    				end case;
    				
    			end case;
    				
    			
    			if(CUSTOMER_TRYING_HELP_ALTERA = '1') then
           	
    				ALTERA_SUPPORT_BLAMES_THE_CUSTOMER <= '1';
    			
    			else
    			
    				ALTERA_SUPPORT_BLAMES_THE_CUSTOMER <= '0';
           	
    			end if;
    			
    			
    			if(Altera_Customers = "0100") then
    			
    				ALTERA_CLOSE_THE_DOORS <= '1';
    			
    			else
           	
    				ALTERA_CLOSE_THE_DOORS <= '0';
    				
    			end if;			
    			 	
           	end process;
           	       	
    end very_bad_behavior; -- I hope...

    See that intentionally i put a "end case" instead "end if", and i get this error:

    Error (10500): VHDL syntax error at fool.vhd(52) near text "case"; expecting "if"

    So the first thing that the user think is: "Ok i will click on this error to see what happened!". Arriving in the line the user reads "end case;"... and think: "Oh my god this compiler is crazy! It wants i put a "if" NEAR "case", wtf?"

    So until this message error is WRONG! You could solve that easily change it to:

    Error (10500): VHDL syntax error at fool.vhd(52) ; expecting "if" instead "case"

    So i ask you: Is hard do that? No it is not.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    The decision to drive the next state is up to the way you want it to be.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi Daixiwen,

    My code was perfect, your site that ate the tabs after i did ctrl+c ctrl+v from Quartus (one more thing to solve). I tried to show you this error of Quartus because i believe that Altera(now Intel) can fix things like that and so get more adepts to use its tools. I never used this forum of Altera but i liked of one thing, you answers very fast! I confess that i did not have a real doubt, but a complain. Good companies receive well the criticisms, but i did not see that here. I hope that Altera could improve that and create a channel to complains and criticisms, and not just create but encourage the users to help Altera to build better tools.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi Marcos,

    As you start to use various vendor tools, you'll find they all have shortcomings. The best way to track down annoying errors is often to try (at least) two tools. I typically start with Modelsim for HDL development, and then switch to synthesis once I have a testbench working. Quartus sometimes catches errors that Modelsim misses, eg., signals in sensitivity lists is one that I sometimes see.

    That being said, Modelsim is not fault-free. This week I had QuestaSim crashing repeatedly with a Xilinx BRAM/FIFO model and the solution was to add "-t ps" to the command-line. This argument is often needed for PLLs, but I hadn't bumped into it for RAM, and was not expecting the tool to crash with a floating-point error.

    Bottom-line, the tools have bugs, and you figure out how to deal with them. As for coding, after you've made the some coding error a few times, you recognize the solution to the error message (whether that message is actually useful or not!).

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi Dave,

    Thanks for sharing your experiences. Im not a full time VHDL developer, and i never knew one too. In general a hardware developer, develops software too, and uses about 10, 20 or more software tools to do his work. So, like developers of systems we need to claim to better tools because our time is finite, and precious.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    So, like developers of systems we need to claim to better tools because our time is finite, and precious.

    --- Quote End ---

    Agreed. When I find a bug, or have a suggestion for tool improvements, I typically file a Service Request with Altera. A well written request, eg., one with an example demonstrating the issue, generally aids in getting good feedback.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hi Daixiwen,

    My code was perfect, your site that ate the tabs after i did ctrl+c ctrl+v from Quartus (one more thing to solve).

    --- Quote End ---

    Sorry I didn't meant your code wasn't good, but as in any forum, you need to put some code tags in order to prevent the forum engine from trying to reformat the text. The code tags just say that we want to keep the spaces as they were written and don't want the web server to mess with them.

    --- Quote Start ---

    I tried to show you this error of Quartus because i believe that Altera(now Intel) can fix things like that and so get more adepts to use its tools. I never used this forum of Altera but i liked of one thing, you answers very fast! I confess that i did not have a real doubt, but a complain. Good companies receive well the criticisms, but i did not see that here. I hope that Altera could improve that and create a channel to complains and criticisms, and not just create but encourage the users to help Altera to build better tools.

    --- Quote End ---

    The problem is that this forum is not an official way to contact Altera about those matters. They hardly ever read it and you'll see mostly here other Altera users like us. If you want to make a suggestion to Altera, file up a service requested, as we have suggested. And yes our answers to your initial message may have been a bit negative, but calling a compiler "so bad" and "crap" twice because it uses the word "near" instead of "exactly there" in an error message isn't the best way to start a constructive discussion imho.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Thanks everyone!

    I sent this issue to Request Service and i hope that now, after all these years, and yours and hours lost by customers around the world, this problem will be solved! Whoopee!!!!!!!

    The request number is# 11288436