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13 years agoError 10500: VHDL Syntax
I am working on a code for a basic vending machine that will give out a product at 75cents
BUt for some reason I dont know how to fix this syntax error
Library ieee;
Use ieee.numeric_std.all;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity Lab06 is
Port (
Clock :IN std_logic;
Reset_n :IN std_logic;
Quarter_in :IN std_logic;
Dime_in :IN std_logic;
Nickel_in :IN std_logic;
Pennny_in :IN std_logic;
Coin_Return :IN std_logic);
End Lab06;
Architecture Behavior Of Lab06 is
Signal int_counter: std_logic_vector(25 downto 0);
Constant MAXVALUE: std_logic_vector(25 downto 0):= "10111110101111000010000000"; --One Second Count
-------------------------------------------------------------------------------------------------
Type State_type is (wait1, penny, dime, nickel, quarter, enough, excess, vend, change);
Signal current_state,next_state: state_type;
Signal Money: std_logic_vector(6 downto 0);
Signal Red_Bull: std_logic;
Signal Change_Back: std_logic;
Begin
Counter_Clock:Process (clock, reset_n)
Begin
If reset_n = '0' Then
Int_counter <= (Others => '0');
Elsif (rising_edge(clock)) Then
If int_counter = MAXVALUE Then
int_counter <= (Others => '0');
Else
int_counter <= int_counter + '1';
End If;
End If;
End Process;
Sync:Process (clock, reset_n)
Begin
If (reset_n = '0')then
Current_state <= Wait1;--Wait1 is the default state_type
Elsif(rising_edge(clock))Then
If (int_counter = MAXVALUE)Then
Current_state <=next_state;-- Advance the state(Red Bull)machine
End If;
End If;
End Process;
Comb:Process(int_counter,current_state, Quarter_in, Dime_in, Nickel_in, Pennny_in, money, Coin_Return)
Begin
If (int_counter = MAXVALUE) Then
Case(current_state)is
When wait1=>
If (money = "0000000")Then -- No money in vending machine
next_state <= Wait1;
If (Quarter_in = '1')Then -- Money is inserted
next_state <= Quarter;
If (Dime_in = '1')Then
next_state <= Dime;
If (Nickel_in = '1')Then
next_state <= Nickel;
If (Pennny_in = '1')Then
next_state <= Penny;
If (money >= "1001011")Then
next_state <= Enough;
If(Coin_Return = '1')Then
next_state <= Change;
Else
next_state <=Wait1;
End If;
----------------------------------------------------------------- After Quarter Inserted, next step
When Quarter =>
Next_state <= Wait1;
----------------------------------------------------------------- After Dime Inserted, next step
When Dime =>
Next_state <= Wait1;
----------------------------------------------------------------- After Nickel Inserted, next step
When Nickel =>
Next_state <= Wait1;
----------------------------------------------------------------- After Penny Inserted, next step
When Penny =>
Next_state <= Wait1;
When Enough =>
If (money >= "1001011")Then
Next_state <= Excess;
Else
Next_state <= vend;
End If;
When Excess =>
Next_state <= vend;
When vend =>
Next_state <= Wait1;
When Change =>
Next_state <= Wait1;
When OTHERS =>
next_state <= Wait1;
End Case;
End If;
End Process;
----------------------------------------------------------------- Money calculation
Money_Calc:Process(Current_state, money)
Begin
Case (current_state) is
When wait1 =>
Money <= Money;
When Quarter =>
Money <= Money + "0011001";
When Dime =>
Money <= Money + "0001010";
When Nickel =>
Money <= Money + "0000101";
When Penny =>
Money <= Money + "0000001";
When Enough =>
Money <= money;
When Excess =>
Money <= Money;
When vend =>
Money <= Money - "1001011";
When change =>
Money <= "0000000";
When OTHERS =>
Money <= Money;
End Case;
End Process;
End Behavior;
The errors I am getting are Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 12.0 Build 178 05/31/2012 SJ Full Version Info: Processing started: Wed Oct 31 15:32:29 2012 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab06 -c Lab06 Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (12021): Found 2 design units, including 1 entities, in source file hex_display.vhd Info (12022): Found design unit 1: Hex_Display-Structure Info (12023): Found entity 1: Hex_Display Error (10500): VHDL syntax error at Lab06.vhd(108) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(111) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(114) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(117) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(120) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(126) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(128) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(130) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(132) near text "When"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at Lab06.vhd(134) near text "Case"; expecting "if" Error (10500): VHDL syntax error at Lab06.vhd(136) near text "Process"; expecting "if" Error (10500): VHDL syntax error at Lab06.vhd(139) near text "Begin"; expecting ":=", or "<=" Error (10500): VHDL syntax error at Lab06.vhd(162) near text "Process"; expecting "if" Info (12021): Found 0 design units, including 0 entities, in source file lab06.vhd Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 13 errors, 0 warnings Any assistance would be very helpful.