Take a look in my code, i did specially to show the ERROR of compiler message:
entity ALTERA_COMPANY is
port(
CUSTOMER_TRYING_HELP_ALTERA: in std_logic;
TIME_OF_CUSTOMERS: in std_logic;
ALTERA_START: in std_logic;
ALTERA_SUPPORT_BLAMES_THE_CUSTOMER: out std_logic;
ALTERA_CLOSE_THE_DOORS: out std_logic
);
end ALTERA_COMPANY;
architecture very_bad_behavior of ALTERA_COMPANY is
-- Contador de elementos a serem processados
signal Altera_Customers: std_logic_vector(3 downto 0);
begin
process(CUSTOMER_TRYING_HELP_ALTERA,TIME_OF_CUSTOMERS)
begin
if(TIME_OF_CUSTOMERS='1' and TIME_OF_CUSTOMERS'event) then
case ALTERA_START is
when '0' =>
if(CUSTOMER_TRYING_HELP_ALTERA = '1' and Altera_Customers /= "0100") then
Altera_Customers <= Altera_Customers - 1;
end if;
when '1' =>
Altera_Customers <= "1111";
end case;
end case;
if(CUSTOMER_TRYING_HELP_ALTERA = '1') then
ALTERA_SUPPORT_BLAMES_THE_CUSTOMER <= '1';
else
ALTERA_SUPPORT_BLAMES_THE_CUSTOMER <= '0';
end if;
if(Altera_Customers = "0100") then
ALTERA_CLOSE_THE_DOORS <= '1';
else
ALTERA_CLOSE_THE_DOORS <= '0';
end if;
end process;
end very_bad_behavior; -- I hope...
See that intentionally i put a "end case" instead "end if", and i get this error:
Error (10500): VHDL syntax error at fool.vhd(52) near text "case"; expecting "if"
So the first thing that the user think is: "Ok i will click on this error to see what happened!". Arriving in the line the user reads "end case;"... and think: "Oh my god this compiler is crazy! It wants i put a "if" NEAR "case", wtf?"
So until this message error is WRONG! You could solve that easily change it to:
Error (10500): VHDL syntax error at fool.vhd(52) ; expecting "if" instead "case"
So i ask you: Is hard do that? No it is not.