Error 10500 near text ¨´¨; epecting ¨;

Hello all,

I need help,

I can see any reasons why I am getting en error:

Error (10500): VHDL syntax error at Adder.vhd(49) near text ¨´¨; expecting ¨;¨

The error points to line: outBuffer(8) <= ´0´; in my code.

Here is my complete codes:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

use ieee.std_logic_misc.all;

entity adder8bits is

port (

clk : in std_logic;

inputSignal0 : in std_ulogic_vector(7 downto 0);

inputSignal1 : in std_ulogic_vector(7 downto 0);

outSignal : out std_ulogic_vector(8 downto 0)

);

end entity adder8bits;

architecture rtl of adder8bits is

signal bitBuffer0 : std_ulogic_vector(7 downto 0);

signal bitBuffer1 : std_ulogic_vector(7 downto 0);

signal outBuffer : std_ulogic_vector(8 downto 0);

signal signalBuffer0 : std_ulogic_vector(7 downto 0);

signal signalBuffer1 : std_ulogic_vector(7 downto 0);

signal count : integer;

begin

process(clk,signalBuffer0,signalBuffer1,bitBuffer0,bitBuffer1,outBuffer,outSignal)

begin

if rising_edge(clk) then

signalBuffer0(7 downto 0) <= inputSignal0(7 downto 0);

signalBuffer1(7 downto 0) <= inputSignal1(7 downto 0);

count <= 0;

outSignal <= outBuffer;

elsif falling_edge(clk) then

bitBuffer0(7 downto 0) <= signalBuffer0(7 downto 0) xor signalBuffer1(7 downto 0);

bitBuffer1(7 downto 0) <= signalBuffer0(7 downto 0) and signalBuffer1(7 downto 0);

outBuffer(7 downto 0) <= bitBuffer0(7 downto 0);

outBuffer(8) <= ´0´;

for count in 0 to 6 loop

if bitBuffer0(count) = ´0´ and bitBuffer1(count) = ´1´ and bitBuffer0(count+1) = ´0´ then

bitBuffer0(count+1) <= ´1´;

outBuffer(count) <= ´0´;

elsif bitBuffer0(count) = ´0´ and bitBuffer1(count) = ´1´ and bitBuffer0(count+1) = ´0´ then

bitBuffer1(count+1) <= ´1´;

outBuffer(count) <= ´0´;

elsif bitBuffer0(count) = ´1´ and bitBuffer1(count) = ´1´ and bitBuffer0(count+1) = ´0´ then

bitBuffer0(count+1) <= ´1´;

outBuffer(count) <= ´1´;

end if;

end loop;

if bitBuffer0(7) = ´0´ and bitBuffer1(7) = ´1´ then

outBuffer(count) <= ´1´;

elsif bitBuffer0(7) = ´1´ and bitBuffer1(7) = ´1´ then

outBuffer(count) <= ´1´;

end if;

end if

end process;

end rtl;

I have plenty more of the same error.

A new pair of eyes will be helpful, to see where is causing the error.

Thank you.