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Altera_Forum
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13 years ago

Error 10500 near text ¨´¨; epecting ¨;

Hello all, I need help, I can see any reasons why I am getting en error: Error (10500): VHDL syntax error at Adder.vhd(49) near text ¨´¨; expecting ¨;¨ The error points to line: out...
Altera_Forum's avatar
Altera_Forum
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13 years ago

another note - you cannot use both rising_edge and falling_edge in the same process for synthesisable VHDL inside FPGAs.