Error 10500 --> Did I ruin my schematic file?

Hi everybody,

I have seen that quite a few threads have been opened concerning Error 10500. But my error seems somehow different and since I have to finish my project in the next month and I am a beginner I would like to seek your help.

I have designed a perfectly working CPLD Design using the Block Editor. I have compiled this design plenty of times and did a lot of simulations with it. The next step would have been to assign the Inputs/Outputs with the Pin Planner. Somehow I was playing a bit around in the Pin Planner and overwrote my vhd. file. Since then, whenever I try to compile my design Quartus shows (during Analysis & Settings)

Error 10500: VHDL Syntax error at interlocktimes.vhd(24) near text "Configuration"; expecting an identifier ("configuration" is a reserved keyword), or "constant", or "file", or "signal", or "variable".

The code line with the mistake seems to be:

Configuration: in std_logic

I figure, that "Configuration" is not a valid name for an input. But why did the Compilation work before without any problem if thats suddenly the problem?

I am kind of lost, since I can't open the Schematic file anymore and I don't have a backup version and would like to fix this.

Can you tell me how I can fix this problem and reach my Schematic file and work with that again?

Thanks a lot!