--- Quote Start ---
a and b are std_logic_vectors. You cannot do arithmatic with them
you need to convert them to unsigned or signed types before you can do arithmatic. You probably want to declare them as signed or unsigned in the first place, or you will need a lot of type conversion:
p := std_logic_vector( unsigned('0' & a) + unsigned('0' & b) );
if p, a and b were all declared as unsigned:
a : unsigned(3 downto 0);
type conversions wouldnt be needed:
p := ('0'&a) + ('0'&b);
Btw, why are you using "after" keyword. It is not synthesisable and is for simulation only.
--- Quote End ---
Thank you! Changed it and now i am not getting the fault anymore ! :)
But what i now get is that it adds an latch on some outputs..
Warning (10631): VHDL Process Statement warning at ADD_SUBB.vhd(44): inferring latch(es) for signal or variable "ovf", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at ADD_SUBB.vhd(44): inferring latch(es) for signal or variable "sign", which holds its previous value in one or more paths through the process
I don't want that in my design.. Why is it doing this? I did give all outputs a path ?
Thank you!
-- Library Declaration
LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
-- Entity Declaration
entity ADD_SUBB is
port
(
a : in std_logic_vector (3 downto 0); -- Input A
b : in std_logic_vector (3 downto 0); -- Input B
sel : in std_logic; -- ADD/SUB, Go's to mux to choose if it is SUB or ADD.
r : out std_logic_vector (3 downto 0); -- Result of ADD or SUB
ovf : out std_logic; -- Overflow, when result is above 15
sign : out std_logic -- + or -
);
end ADD_SUBB;
-- Architecture Body
architecture RTL of ADD_SUBB is
signal c : std_logic_vector (3 downto 0); -- sum of adder
signal d : std_logic; -- overflow of adder
signal e : std_logic_vector (3 downto 0); -- sum of subtractor
signal f : std_logic; -- sign bit +/-
Begin
process (a,b) -- Add function.
variable p: std_logic_vector (4 downto 0 );
begin
p := std_logic_vector(unsigned('0'&a) + unsigned('0'&b));
c <= p(3 downto 0) after 5ns;
d <= p(4) after 5ns;
end process;
process(a,b) -- Sub function.
variable p: std_logic_vector (4 downto 0 );
begin
p := std_logic_vector(unsigned('0'&a) - unsigned('0'&b));
e <= p(3 downto 0) after 5ns;
f <= p(4) after 5ns;
end process;
process(c,d,e,f,sel) -- Decoder(mux)
begin
if sel = '0' then
r <= c;
ovf <= d;
elsif sel = '1' then
r <= e;
sign <= f;
else
r <= c;
ovf <= d;
sign <= f;
end if;
end process;
end architecture;
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